中英文资料外文翻译
(文档含英文原文和中文翻译)
外文资料
A New Contact-less Smart Card IC Using an On-Chip Antenna and an
Asynchronous Micro-controller
Abstract—This paper describes a new generation of Contact-less Smart Card Chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the IS0 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit micro-controller. Beyond the Contact-less Smart Card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-- m technology from ST-Micro-electronics.
Index Terms— Asynchronous processor, coil-on-chip, quasi-delay insensitive circuits, Smart Cards, system-on-chip.
I.INTRODUCTION
The Smart Card market enters a new era, with a booming number of applications in various domains and new countries willing to use this technology.
Smart Cards are becoming more and more ubiquitous and the trend is to integrate a card reader in all kind of equipment (PCs,PDAs, mobile phones, etc.). E-commerce, citizen administration, and others could be, through the Internet, good vehicles to allow service providers to develop new services using the Smart Card as a high-security key element.
In this context, contact-less Smart Cards should play an important part. The absence of contact induces lower maintenance cost, improves ease of use, reliability, and, therefore, end-user satisfaction. They are declined in several types according to the location of the antenna. It can be on the card, on the module,or integrated directly on the chip. This later technique significantly decreases card fabrication cost. Moreover, as the user still inserts his card in a reader slot, transactions remain as safe as when using cards with contacts.
Since most applications require low-cost low-power systems, the goal of this work is to integrate on a single chip an antenna, an ISO14443 compliant radio-frequency emitter/receiver, together with an asyn
chronous micro-controller. Integrating the whole system on silicon should pave the way to new reliable low-cost Contact-less Smart Card chips.
These main key technologies used to design this new Smart Card chip are presented in Section II. The Smart Card chip de-sign is detailed in Section III, and the design methodology is briefly described in Section IV. Experimental results are given in Section V.
II.INNOVATION
The innovation of this chip lies in the association on the same die of two key technologies [9]: an integrated power reception system with an on-chip coil [5], and an 8-bit CISC QDI asynchronous micro-controller [8]. This association enables us to take advantage of the asynchronous logic properties in order to decrease the design constraints of the integrated power reception system and also to increase the working domain of the digital processing part.
In fact, the asynchronous logic has three interesting advantages valuable for the Contact-less Smart Card application considered here [6], [7]. Instead of being clock driven, asynchronous circuits are data driven which results in a lower mean-power consumption. Instead of implementing a central control unit, asynchronous circuits implement a distributed control system which results in smaller current pea
ks and then lower electromagnetic emission because the electrical activity is spread over time. Finally, instead of being ―clock timed‖,asynchronous circuits are self-timed which enables an automatic regulation of the performance. Hence, QDI asynchronous circuits are not sensitive to voltage variations, and runs at their maximum speed with respect to the power received.
Since the QDI 8-bit micro-controller is so robust with respect to the power supply variations (see Section III), the design of the power reception system is made easier: lower average power delivered, as well as the peak power, and simplified regulation of the supply voltage. This not only makes the design easier, but also decreases the area (smaller VDD smoothing capacitance).Finally, because of its low current peaks the QDI asynchronous micro-controller does not interfere with the load modulation used in the ISO 14 443 standard for the communication between the card and the reader. This enables the micro-controller to run while the chip is transferring data to the reader which decreases the complexity of the software and then the memory space requirements.
III.SMART CARDCHIP DESIGN
The Smart Card chip is composed of four main blocks(Fig. 1). The RF front-end recovers power from the integrated antenna, which forms a transformer with the external reader antenna. The recovered po
wer is then stabilized and supplies the whole chip: the asynchronous micro-controller and a synchronous dedicated interface between the RF block and the asynchronous circuit.
Fig. 1. Chip architecture.
This interface is driven by a reception-enable signal (REN)controlled by the micro-controller. In reception mode, the RF interface demodulates data sent by the reader. In emission mode,data are sent to the reader using a load modulation. The system is ISO14443-B compliant [10].
When the Smart Card is inserted in the reader slot, as soon as the stabilized supply reaches a sufficient level, reset is activated by the RF interface. The micro-controller executes the boot program c
ontained in ROM and then waits for data coming from the reader. The communication between the reader and the Smart Card is functionally asynchronous. The combination of the REN signal and the start and stop bits (the communication between the reader and the chip is made on an asynchronous mode, with start and stop bits), encapsulating the transmitted byte implements a half-duplex communication.
A. Analog Block Design
Since there are no contacts, power and data are recovered from RF signals emitted by the reader. The analog block is in charge of
1) powering the chip;
2) demodulating/modulating data from/to the reader;
3) recovering the clock used in the synchronous/asynchronous interface.
Compared to other contact-less technologies [7], the card is inserted in a slot which ensures that the distance chip reader is kept constant and small: the variations in distance are within millimeters. This enables the integration of the coil on-chip. Then,there is no need for the voltage which is recovered fro
m the RF power to be very well regulated,as it is the case for contact-less cards which operate on a ―touch and go basis.‖ The design of the power management and analog block circuitry is accordingly simplified.
The block diagram of the RF front-end is described in Fig. 2.It is built of the following parts.
1) The full wave rectifier (FWR) is a bridge composed of nMOS and pMOS transistors. The electro-motive-force(EMF) induced in the on-chip antenna is applied to the FWR inputs. The negative output is connected to the bulk and the positive output is connected to a 500 pF smoothing capacitor. It delivers the nonregulated voltage NRV to the chip.
Fig. 2. RF front-end block diagram
2) The clock recovery block extracts the 13.56-MHz clock from the RF carrier signal. For this purpose, the input of a Schmidt trigger is connected to one of the two antenna terminals.
3) The power-on detector. This block is composed of a voltage reference, a differential comparator and filters to reject modulation parasitics. It triggers a RESET when the NRV reaches a given level.
4) The data demodulator is based on NRV amplitude transitions due to NRZ coded transmission from reader to chip.The data demodulator extracts the data mixed with NRV,by detecting negative and positive transitions. The two outputs drive the inputs of an RS latch which makes the data available to the interface.
5) The load modulator is built of a resistor (Rmod, see Fig. 3)switched by an nMOS transistor controlled by the data to be sent to the reader. It induces an amplitude modulation in the inductor antenna. In emission, the modulator has to modulate the power absorbed by the chip at an 847-kHz BPSK rhythm. This is made by a modulation of I(NRV),2I∆. This induces an EMF in the reader solenoid. The EMF value is
F
V∆
∆
=
∏
2I
2
M
*
controller翻译中文
*
*
where is the mutual inductor and the carrier frequency.
Fig. 3. Power management
6) The current generator is associated with a zener diode to achieve power regulation.
As we want information to be transmitted to the reader when the microcontroller is running, and since a load modulation is used, care must be taken to the dynamic current consumption of the micro-controller which can induce NRV current variations and then corrupt the communication. To prevent this phenomena from occurring, a constant current source is used to feed the logic together with a 2-V shunt voltage stabilizer. The constant current generator is designed to provide the maximum current needed by the logic part. This mechanism ensures a constant NRV current and therefore avoids parasitic load modulation that could be induced by software running in the micro-controller(Fig. 4).
Fig 4.VDD and I(NRV)versus I(load).
In this prototype, the current generator is designed to deliver 15 mA in order to supply the micro-controller as well as an external nonvolatile memory included in a demonstrator under development.
B. Synchronous/Asynchronous Interface
The block diagram of the interface is presented in Fig. 5. It is composed of a divider, a BPSK modulator and a block which formats the data coming from the external reader and from the micro-controller.The RF 13.56-MHz carrier is recovered and divided to provide a 847-kHz signal used to
clock the interface. On the RF interface side, bytes are encapsulated with start and stop bits which are then received or emitted sequentially at the 847-kHz bit rate. On the micro-controller side, an asynchronous four-phase bundle-data protocol is used (8-bit data, request and acknowledge signals) to control data exchange with the QDI asynchronous micro-controller.
Fig. 5. Interface block diagram.
This interface implements two types of conversion: protocol conversion and serial/parallel or parallel/serial conversions. It is designed as a synchronous finite state machine and therefore, some timing assumptions are made when sampling asynchronous control signals like P5req and P4ack. When a data has to be emitted from the card, the REN signal is disabled by the micro-controller which asks for writing into the interface by asserting the P5req signal. The interface answers by asserting P5
ack. The four-phase handshake protocol then completes with two return-to-zero phases as soon as the one byte buffer is empty. When receiving data from the reader, the REN signal is driven high and the micro-controller is ready to receive an input byte by asserting the P4ack signal. The interface answers rising the P4req signal as soon as a byte is available from the receiver. The handshake then completes with the return-to-zero phase.
The handshake protocol ensures that both the micro-controller and the interface are available to accept and transmit a byte in emission or reception. Thus, the micro-controller will be idled as long as the interface