efm8系列单⽚机c语⾔编程,EFM8单⽚机⽤Keil编程，头⽂件
怎么写？
到头⽂件了，如下：(芯⽚为Silicon Laboratories的EFM8UB10F16G)
需要⽤到P1⼝，头⽂件中这样定义P1⼝“SI_SFR (P1, 0x90); ///< Port 1 Pin Latch ” 怎么跟reg51.h中“sfr P1 =
0x90;”不⼀样？另外，在keil中输P1，却还是报P1未定义错误？
//------------------------------------------------------------------------------
// Copyright 2014 Silicon Laboratories, Inc.
// All rights reserved. This program and the accompanying materials
// are made available under the terms of the Silicon Laboratories End User
// License Agreement which accompanies this distribution, and is available at
// Original content and implementation provided by Silicon Laboratories.
//------------------------------------------------------------------------------
//Supported Devices:
// EFM8UB10F16G
// EFM8UB10F16G
// EFM8UB10F8G
// EFM8UB11F16G
#ifndef SI_EFM8UB1_DEFS_H
#define SI_EFM8UB1_DEFS_H
#include
//-----------------------------------------------------------------------------
// Register Definitions
/
/-----------------------------------------------------------------------------
SI_SFR (ACC, 0xE0); ///< Accumulator
SI_SFR (ADC0AC, 0xB3); ///< ADC0 Accumulator Configuration
SI_SFR (ADC0CF, 0xBC); ///< ADC0 Configuration
SI_SFR (ADC0CN0, 0xE8); ///< ADC0 Control 0
SI_SFR (ADC0CN1, 0xB2); ///< ADC0 Control 1
SI_SFR (ADC0GTH, 0xC4); ///< ADC0 Greater-Than High Byte
SI_SFR (ADC0GTL, 0xC3); ///< ADC0 Greater-Than Low Byte
SI_SFR (ADC0H, 0xBE); ///< ADC0 Data Word High Byte
SI_SFR (ADC0L, 0xBD); ///< ADC0 Data Word Low Byte
SI_SFR (ADC0LTH, 0xC6); ///< ADC0 Less-Than High Byte
SI_SFR (ADC0LTL, 0xC5); ///< ADC0 Less-Than Low Byte
SI_SFR (ADC0MX, 0xBB); ///< ADC0 Multiplexer Selection
SI_SFR (ADC0PWR, 0xDF); ///< ADC0 Power Control
SI_SFR (ADC0TK, 0xB9); ///< ADC0 Burst Mode Track Time编程语言下载
SI_SFR (B, 0xF0); ///< B Register
SI_SFR (CKCON0, 0x8E); ///< Clock Control 0
SI_SFR (CKCON1, 0xA6); ///< Clock Control 1
SI_SFR (CLKSEL, 0xA9); ///< Clock Select
SI_SFR (CMP0CN0, 0x9B); ///< Comparator 0 Control 0
SI_SFR (CMP0CN1, 0x99); ///< Comparator 0 Control 1
SI_SFR (CMP0MD, 0x9D); ///< Comparator 0 Mode
SI_SFR (CMP0MX, 0x9F); ///< Comparator 0 Multiplexer Selection SI_SFR (CMP1CN0, 0xBF); ///< Comparator 1 Control 0
SI_SFR (CMP1CN1, 0xAC); ///< Comparator 1 Control 1
SI_SFR (CMP1MD, 0xAB); ///< Comparator 1 Mode
SI_SFR (CMP1MX, 0xAA); ///< Comparator 1 Multiplexer Selection SI_SFR (CRC0CN0, 0xCE); ///< CRC0 Control 0
SI_SFR (CRC0CN1, 0x86); ///< CRC0 Control 1
SI_SFR (CRC0CNT, 0xD3); ///< CRC0 Automatic Flash Sector Count SI_SFR (CRC0DAT, 0xDE); ///< CRC0 Data Output
SI_SFR (CRC0FLIP, 0xCF); ///< CRC0 Bit Flip
SI_SFR (CRC0IN, 0xDD); ///< CRC0 Data Input
SI_SFR (CRC0ST, 0xD2); ///< CRC0 Automatic Flash Sector Start SI_SFR (DERIVID, 0xAD); ///< Derivative Identification
SI_SFR (DEVICEID, 0xB5); ///< Device Identification
SI_SFR (DPH, 0x83); ///< Data Pointer High
SI_SFR (DPL, 0x82); ///< Data Pointer Low
SI_SFR (EIE1, 0xE6); ///< Extended Interrupt Enable 1
SI_SFR (EIE2, 0xCE); ///< Extended Interrupt Enable 2
SI_SFR (EIP1, 0xF3); ///< Extended Interrupt Priority 1 Low
SI_SFR (EIP1H, 0xF5); ///< Extended Interrupt Priority 1 High
SI_SFR (EIP2, 0xF4); ///< Extended Interrupt Priority 2
SI_SFR (EIP2H, 0xF6); ///< Extended Interrupt Priority 2 High
SI_SFR (EMI0CN, 0xE7); ///< External Memory Interface Control
SI_SFR (FLKEY, 0xB7); ///< Flash Lock and Key
SI_SFR (HFO0CAL, 0xC7); ///< High Frequency Oscillator 0 Calibration SI_SFR (HFO1CAL, 0xD6); ///< High Frequency Oscillator 1 Calibration SI_SFR (HFOCN, 0xEF); ///< High Frequency Oscillator Control
SI_SFR (I2C0CN0, 0xBA); ///< I2C0 Control
SI_SFR (I2C0DIN, 0xBC); ///< I2C0 Received Data
SI_SFR (I2C0DOUT, 0xBB); ///< I2C0 Transmit Data
SI_SFR (I2C0FCN0, 0xAD); ///< I2C0 FIFO Control 0
SI_SFR (I2C0FCN1, 0xAB); ///< I2C0 FIFO Control 1
SI_SFR (I2C0FCT, 0xF5); ///< I2C0 FIFO Count
SI_SFR (I2C0SLAD, 0xBD); ///< I2C0 Slave Address
SI_SFR (I2C0STAT, 0xB9); ///< I2C0 Status
SI_SFR (IE, 0xA8); ///< Interrupt Enable
SI_SFR (IP, 0xB8); ///< Interrupt Priority
SI_SFR (IPH, 0xF2); ///< Interrupt Priority High
SI_SFR (IT01CF, 0xE4); ///< INT0/INT1 Configuration
SI_SFR (LFO0CN, 0xB1); ///< Low Frequency Oscillator Control
SI_SFR (P0, 0x80); ///< Port 0 Pin Latch
SI_SFR (P0MASK, 0xFE); ///< Port 0 Mask
SI_SFR (P0MAT, 0xFD); ///< Port 0 Match
SI_SFR (P0MDIN, 0xF1); ///< Port 0 Input Mode
SI_SFR (P0MDOUT, 0xA4); ///< Port 0 Output Mode
SI_SFR (P0SKIP, 0xD4); ///< Port 0 Skip
SI_SFR (P1, 0x90); ///< Port 1 Pin Latch
SI_SFR (P1MASK, 0xEE); ///< Port 1 Mask
SI_SFR (P1MAT, 0xED); ///< Port 1 Match
SI_SFR (P1MDIN, 0xF2); ///< Port 1 Input Mode
SI_SFR (P1MDOUT, 0xA5); ///< Port 1 Output Mode
SI_SFR (P1SKIP, 0xD5); ///< Port 1 Skip
SI_SFR (P2, 0xA0); ///< Port 2 Pin Latch
SI_SFR (P2MASK, 0xFC); ///< Port 2 Mask
SI_SFR (P2MAT, 0xFB); ///< Port 2 Match
SI_SFR (P2MDIN, 0xF3); ///< Port 2 Input Mode
SI_SFR (P2MDOUT, 0xA6); ///< Port 2 Output Mode
SI_SFR (P2SKIP, 0xCC); ///< Port 2 Skip
SI_SFR (P3, 0xB0); ///< Port 3 Pin Latch
SI_SFR (P3MDIN, 0xF4); ///< Port 3 Input Mode
SI_SFR (P3MDOUT, 0x9C); ///< Port 3 Output Mode
SI_SFR (PCA0CENT, 0x9E); ///< PCA Center Alignment Enable
SI_SFR (PCA0CLR, 0x9C); ///< PCA Comparator Clear Control
SI_SFR (PCA0CN0, 0xD8); ///< PCA Control
SI_SFR (PCA0CPH0, 0xFC); ///< PCA Channel 0 Capture Module High Byte SI_SFR (PCA0CPH1, 0xEA); ///< PCA Channel 1 Capture Module High Byte SI_SFR (PCA0CPH2, 0xEC); ///< PCA Channel 2 Capture Module High Byte SI_SFR (PCA0CPL0, 0xFB); ///< PCA Channel 0 Capture Module Low Byte SI_SFR (PCA0CPL1, 0xE9); ///< PCA Channel 1 Capture Module Low Byte SI_SFR (PCA0CPL2, 0xEB); ///< PCA Channel 2 Capture Module Low Byte SI_SFR (PCA0CPM0, 0xDA); ///< PCA Channel 0 Capture/Compare Mode SI_SFR (PCA0CPM1, 0xDB); ///< PCA Channel 1 Capture/Compare Mode SI_SFR (PCA0CPM2, 0xDC); ///< PCA Channel 2 Capture/Compare Mode SI_SFR (PCA0H, 0xFA); ///< PCA Counter/Timer High Byte
SI_SFR (PCA0L, 0xF9); ///< PCA Counter/Timer Low Byte
SI_SFR (PCA0MD, 0xD9); ///< PCA Mode
SI_SFR (PCA0POL, 0x96); ///< PCA Output Polarity
SI_SFR (PCA0PWM, 0xF7); ///< PCA PWM Configuration
SI_SFR (PCON0, 0x87); ///< Power Control
SI_SFR (PCON1, 0x9A); ///< Power Control 1
SI_SFR (PFE0CN, 0xC1); ///< Prefetch Engine Control
SI_SFR (PRTDRV, 0xF6); ///< Port Drive Strength
SI_SFR (PSCTL, 0x8F); ///< Program Store Control
SI_SFR (PSW, 0xD0); ///< Program Status Word
SI_SFR (REF0CN, 0xD1); ///< Voltage Reference Control
SI_SFR (REG0CN, 0xC9); ///< Voltage Regulator 0 Control
SI_SFR (REG1CN, 0xC6); ///< Voltage Regulator 1 Control
SI_SFR (REVID, 0xB6); ///< Revision Identifcation
SI_SFR (RSTSRC, 0xEF); ///< Reset Source
SI_SFR (SBCON1, 0x94); ///< UART1 Baud Rate Generator Control
SI_SFR (SBRLH1, 0x96); ///< UART1 Baud Rate Generator High Byte
SI_SFR (SBRLL1, 0x95); ///< UART1 Baud Rate Generator Low Byte
SI_SFR (SBUF0, 0x99); ///< UART0 Serial Port Data Buffer
SI_SFR (SBUF1, 0x92); ///< UART1 Serial Port Data Buffer
SI_SFR (SCON0, 0x98); ///< UART0 Serial Port Control
SI_SFR (SCON1, 0xC8); ///< UART1 Serial Port Control
SI_SFR (SFRPAGE, 0xA7); ///< SFR Page
SI_SFR (SFRPGCN, 0xCF); ///< SFR Page Control
SI_SFR (SFRSTACK, 0xD7); ///< SFR Page Stack
SI_SFR (SMB0ADM, 0xD6); ///< SMBus 0 Slave Address Mask
SI_SFR (SMB0ADR, 0xD7); ///< SMBus 0 Slave Address
SI_SFR (SMB0CF, 0xC1); ///< SMBus 0 Configuration
SI_SFR (SMB0CN0, 0xC0); ///< SMBus 0 Control
SI_SFR (SMB0DAT, 0xC2); ///< SMBus 0 Data
SI_SFR (SMB0FCN0, 0xC3); ///< SMBus0 FIFO Control 0
SI_SFR (SMB0FCN1, 0xC4); ///< SMBus0 FIFO Control 1
SI_SFR (SMB0FCT, 0xEF); ///< SMBus0 FIFO Count
SI_SFR (SMB0RXLN, 0xC5); ///< SMBus0 Receive Length Counter SI_SFR (SMB0TC, 0xAC); ///< SMBus 0 Timing and Pin Control SI_SFR (SMOD1, 0x93); ///< UART1 Mode
SI_SFR (SP, 0x81); ///< Stack Pointer
SI_SFR (SPI0CFG, 0xA1); ///< SPI0 Configuration
SI_SFR (SPI0CKR, 0xA2); ///< SPI0 Clock Rate
SI_SFR (SPI0CN0, 0xF8); ///< SPI0 Control
SI_SFR (SPI0DAT, 0xA3); ///< SPI0 Data
SI_SFR (SPI0FCN0, 0x9A); ///< SPI0 FIFO Control 0
SI_SFR (SPI0FCN1, 0x9B); ///< SPI0 FIFO Control 1
SI_SFR (SPI0FCT, 0xF7); ///< SPI0 FIFO Count
SI_SFR (TCON, 0x88); ///< Timer 0/1 Control
SI_SFR (TH0, 0x8C); ///< Timer 0 High Byte
SI_SFR (TH1, 0x8D); ///< Timer 1 High Byte
SI_SFR (TL0, 0x8A); ///< Timer 0 Low Byte
SI_SFR (TL1, 0x8B); ///< Timer 1 Low Byte
SI_SFR (TMOD, 0x89); ///< Timer 0/1 Mode
SI_SFR (TMR2CN0, 0xC8); ///< Timer 2 Control 0
SI_SFR (TMR2CN1, 0xFD); ///< Timer 2 Control 1
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