Understanding DDR3 Serial Presence Detect (SPD) Table

Tuesday, July 17, 2007
Introduction
Since I wrote 揢nderstanding DDR Serial Presence Detect (SPD) Table?in 2003, I have been getting a lot a feedback from readers. I added 揢nderstanding DDR2 Serial Presence Detect (SPD) Table?in 2006.  Some of you told me that you are using these articles to train your employees and to introduce the mysteries SPD concept to your customers. I feel honored by your responses.
Lately, CST has started shipment of a DDR3 EZ Programmer. Since the DD3 DIMM is introduced recently, I think this is the time to add an article for the DDR3 SPD Table. Due to the many more years of development, the DD3 SPD table has definitely got more sophisticated than the original DDR and DDR2 SPD table. Your attention is required to understand and follow through. I will try to use as much layman language as I can to accommodate you all.
Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry. Most people only know it as the little Eeprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite. The SPD data actually provide vital information to the system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with 揟urbo-Tax?type of multiple choices questions. I hope you抣l find it interesting and useful.
Sample Jedec Standard SPD Data Table
Byte 0
Number of Serial PD Bytes Written/ SPD Device Size/ CRC Coverage
（写入的SPD字节数/EERPOM总字节数/CRC覆盖字节范围）
Bit 3 to Bit 0 describes the total size of the serial memory actually used in the EEprom for the Serial Presence Detect data. Bit 6 to Bit 4 describes the number of bytes available in the EEprom device, usually 128byte or 256 byte. On top of that, Bit 7 indicates whether the unique module identifier covered by the CRC encoded on bytes 126 and 127 is based on (0-116byte) or based on (0-125byte)..
(When CST EZ-SPD Programmer is used: Simply select items from 3 tables and automatically calculate the final hex number)
The most common one used is:
Total SPD Bye = 256
CRC Coverage = 0-116Byte
SPD Byte used = 176 Byte
Resulting code is   92h
Byte 1
SPD Revision  （SPD规范版本）
Version  0.0              00h
Revision 0.5              05h
Revision 1.0              10h
Revision 1.1              11h
Revision 1.2              12h 
Byte 2 （DRAM类型）
DRAM Device Type
This refers to the DRAM type. In this case, we are only dealing with DDR3 SDRAM.
DDR3  SDRAM:    0Bh   
Byte 3
Module Type （内存module类型）
This relates to the physical size, and category of memory module.

Undefined                                00h
RDIMM (Registered Long DIMM)    01h
UDIMM (Unbuffered Long DIMM)  02h
SODIMM (Small Outline DIMM)      03h
Byte 4
SDRAM Density and Banks  （DRAM容量和内部bank数）
This byte defines the total density of the DDR3 SDRAM, in bits, and the number of internal banks into which the memory array is divided.
Presently all DDR3 have 8 internal banks.
SDRAM Chip Size 
512Mb          01h
1Gb              02h 
2Gb              03h
4Gb              04h             
Byte 5
SDRAM Addressing （DRAM行列地址线数目）
This byte describes the row addressing and column addressing in the SDRAM Device.

512Mb chips   
13 Row X 10 Column        09h             
13 Row X 12 Column        0Bh
12 Row X 10 Column        01h
1Gb chips       
14 Row X 10 Column        11h
14 Row X 12 Column          13h
13 Row X 10 Column          09h
2Gb chips       
15Row X  10 Column        19h
15 Row X 12 Column        1Bh
14 Row X 10 Column         11h
Byte 6  （预留）
Reserved       00h
Byte 7  （内存module架构）
Module Organization
This byte describes the organization of the SDRAM module; the number of Ranks and the Device Width of each DRAM
(When CST EZ-SPD Programmer is used: Simply select number of Ranks and Device Width. It automatically calculate final hex number)
1 Rank module using X8 chips      01h
2 Rank module using X8 chips       09h
1 Rank module using X4 chips       00h 
2 Rank module using X4 chips       08h
4 Rank module using X8 chips      19h
4 Rank module using X4chips        18h
1 Rank module using X16 chips      02h
2 Rank module using X16 chips      0Ah
Byte 8
Module Memory Bus Width  （内存总位宽）
This refers to the primary bus width of the module plus the additional with provided by ECC
16bit                            01h
32bit                            04h
64bit (no parity)             03h
64bit + ECC (72bit)         0Bh 
Byte 9
Fine timebase (FTB) Dividend / Divisor  （时基）
This byte defines a value in picoseconds that represents the fundamental timebase for fine grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The granularity in picoseconds is derived from Dividend being divided by the Divisor.

Granularity:
2.5ps       52h
5ps          55h                        
Byte 10
Medium Timebase (MTB) Dividend  （时间参数编码所用时基的分子）
Byte 11
Medium Timebase (MTB) Divisor（时间参数编码所用时基的分母）
These byte defines a value in nanoseconds that represents the fundamental timebase for medium grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The two byte forms the Dividend and the Divisor to determine the granularity of the medium timebase.
Granularity 
0.125ns              Byte 10      01h      Byte  11      08h
0.0625ns             Byte 10      01h      Byte  11      0Fh 
Byte 12
Minimum SDRAM Cycle Time (tCK min)  （DRAM颗粒最小时钟周期）
This byte describes the minimum cycle time for the module in medium timebase (MTB) units.
For MTB granularity = 0.125ns (Byte 10 and Byte 11)
DDR3 400Mhz clock (800data rate)                  14h
DDR3 533Mhz clock (1066data rate)                0Fh
DDR3 667Mhz clock (1333data rate)                0Ch
DDR3 800Mhz clock (1600data rate)                0Ah 
Byte 13  （预留）
Reserved            00h
Byte 14
CAS Latencies Supported, Low Byte  （支持CL值范围，低位字节）
(When CST EZ-SPD Programmer is used: Simply select all latencies supported from table. Automatically calculate the hi and low byte hex value base on binary number)
Latency 5.6 supported                06h
Latency 6    supported                04h
Latency 6,7 supported                0Ch
Latency 5, 6, 7, 8 supported        1Eh
Byte 15
CAS Latencies Supported, High Byte  00h    （支持CL值范围，高位字节）
Byte 16
Minimum CAS Latency Time (tAAmin)  （CAS延迟平均时间tAAmin）
Minimum CAS Latency based on medium timebase (MTB) units. tAAmin can be read off SDRAM data sheet.
Based on medium timebase of 0.125ns
tAAmin   
12.5ns         DDR3-800D        64h         
15ns           DDR3-800E        78h
11.25ns       DDR3-1066E      5Ah
13.125ns     DDR3-1066F      69h
15ns           DDR3-1066G      78h
10.5ns         DDR3-1333F      54h
12ns           DDR3-1333G      60h
13.5ns          DDR3-1333H       6Ch
15ns            DDR3-1333J        78h
10ns            DDR3-1600G      50h
11.25ns      DDR3-1600H      5Ah
12.5 ns        DDR3-1600J        64h
13.75ns      DDR3-1600K      6Eh
 
Byte 17
Minimum Write Recovery Time (tWRmin)    （最小写恢复时间tWRmin）
This byte defines the minimum SDRAM write recovery time in medium timebase (MTB) units. This value is read from the DDR3 SDRAM data sheet.
Based on medium timebase of 0.125ns
tWR min       
15ns                        78h
12ns                        60h
16ns                         80h
Byte 18
Minimum RAS# to CAS# Delay time (tRCDmin)  （RAS到CAS的延迟时间tRCDmin）
This byte defines the minimum SDRAM RAS# to CAS# Delay in (MTB) units
Based on medium timebase of 0.125ns
tRCD min   
12.5ns         DDR3-800D        64h         
15ns           DDR3-800E        78h                     
11.25ns       DDR3-1066E      5Ah                   
13.125ns     DDR3-1066F      69h                   
15ns           DDR3-1066G      78h
10.5ns        DDR3-1333F      54h
12ns           DDR3-1333G      60h
15ns           DDR3-1333J        78h
10ns           DDR3-1600G      50h
11.25ns      DDR3-1600H      5Ah
12.5 ns        DDR3-1600J        64h
13.75ns      DDR3-1600K      6Eh
Byte 19
Minimum Row Active to Row Active Delay time (tRRDmin) width的意思中文翻译（ROW激活命令间隔时间tRRDmin）
This byte defines the minimum SDRAM Row Active to Row Active Delay in (MTB) units. This can be read from the SDRAM data sheet.
 Based on medium timebase of 0.125ns
tRRD min   
6.0 ns        30h                               
7.5  ns       3Ch
10  ns        50h
Byte 20
Minimum Row Precharge Delay Time (tRPmin)  （预充电precharge延迟时间tRPmin）
This byte defines the minimum SDRAM Row Precharge Delay in (MTB) units. This can be read from the SDRAM data sheet.
Based on medium timebase of 0.125ns
tRP min       
12.5ns         DDR3-800D        64h         
15ns            DDR3-800E        78h
13.125ns      DDR3-1066F      69h
15ns            DDR3-1066G      78h
10.5ns         DDR3-1333F      54h
12ns            DDR3-1333G      60h
13.5ns         DDR3-1333H      6Ch
15ns            DDR3-1333J        78h
10ns            DDR3-1600G      50h
11.25ns      DDR3-1600H      5Ah
12.5 ns        DDR3-1600J        64h
13.75ns      DDR3-1600K      6Eh
Byte 21
Upper Nibbles for tRAS and tRC  （tRAS和tRC时间的高位字节）
This byte makes up the MSB (upper 4 bits) of the tRAS (bits 3-0) and tRC (bits 7-4) for Byte  22 (tRAS lower byte) and Byte 23 (tRC lower byte). They are in (MTB) units.
Based on medium timebase of 0.125ns
These nibbles represents the value of 256 (in MTB units) for both the tRAS and tRC upper nibble.. Therefore, the value is always 
 11h
Byte 22
Minimum Active to Precharge Delay Time (tRAS min), Least Significant Byte
（激活到预充电延迟时间tRAS的低位字节）
This byte is the lower 8 bits of the 12 bit tRAS value. It is represented in MTB units. The tRAS value can be read from the SDRAM data sheet.
Based on medium timebase of 0.125ns
tRAS min   
37.5ns          DDR3-800D        2Ch         
37.5ns          DDR3-800E        2Ch
37.5ns          DDR3-1066E      2Ch
37.5ns          DDR3-1066F      2Ch
37.5ns          DDR3-1066G      2Ch
36ns            DDR3-1333F      20h
36ns            DDR3-1333G      20h
36ns            DDR3-1333H      20h
36ns            DDR3-1333J        20h
35ns            DDR3-1600G      18h
35ns            DDR3-1600H      18h
35ns            DDR3-1600J        18h
35ns            DDR3-1600K      18h

Byte 23
Minimum Active to Active Refresh Delay Time (tRC min), Least Significant Byte
（激活到激活/刷新的延迟时间tRCmin的低位字节）
This byte is the lower 8 bits of the 12 bit tRC value. It is represented in MTB units. The tRC value can be read from the SDRAM data sheet.
Based on medium timebase of 0.125ns
tRC  min   
50ns                DDR3-800D        90h         
52.5ns              DDR3-800E        A4h
48.75ns            DDR3-1066E      86h
50.625ns          DDR3-1066F      95h
52.5ns              DDR3-1066G      A4h
46.5ns              DDR3-1333F      74h
48ns                 DDR3-1333G      80h
49.5ns              DDR3-1333H      8Ch
51ns                DDR3-1333J        98h
45ns                DDR3-1600G      68h
46.25ns            DDR3-1600H      72h
47.5ns              DDR3-1600J        7Ch
48.75ns            DDR3-1600K      86h
 
Byte 24
Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
 （刷新恢复延迟时间tRFCmin的低位字节）
Byte 25
Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
（刷新恢复延迟时间tRFCmin的高位字节）
These two Byes forms a 16 bit value representing the tRFC value in MTB units.
Based on medium timebase of 0.125ns
tRFC min     
for 512Mb chip  90ns          Byte 24      D0h          Byte 25        02h
for 1Gb chip      110ns          Byte 24      70h           Byte 25      03h
for 2Gb chip      160ns          Byte 24      00h           Byte 25      05h
Byte 26  （写到读命令延迟时间tWTRmin）
Minimum Internal Write to Read Command Delay time (tWTRmin)
This byte defines the minimum SDRAM Internal Write to Read Delay Time in MTB units. This value is read off the data sheet. 
Based on medium timebase of 0.125ns
tWTR min    7.5ns                is for all DDR3 speed bins        3Ch          
Byte 27  （读到预充命令延迟时间tRTP）
Minimum Internal Read to Precharg Command Delay time (tRTPmin)
This byte defines the minimum SDRAM Internal Read to Precharge Command Delay Time in MTB units. This value is read off the data sheet.
Based on medium timebase of 0.125ns
tRTP min    7.5ns                is for all DDR3 speed bins        3Ch         
 
Byte 28  （4激活命令窗口最小时间tFAWmin的高位字节）
Upper Nibbles for tFAW
This byte makes up the most significant bit value (upper 4 bits) of the tFAW (bits 3-0). They are in (MTB) units. This value is read off the SDRAM data sheet.
Based on medium timebase of 0.125ns
For tFAW value of 32ns or higher, the hex value for this byte is      01h
For all tFAW value less than 32ns, the hex value for this byte is      00h
Byte 29  （4激活命令窗口最小时间tFAWmin的低位字节）
Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte
This works with Byte 28 to form a 12-bit value which defines the minimum SDRAM Four Activate Window Delay Time in MTB units. This data is available on the SDRAM data sheet.
Based on medium timebase of 0.125ns
tFAW min   
40.0ns    DDR3-800, 1K page size            40h
50.0ns    DDR3-800, 2K page size            90h
37.5ns    DDR3-1066, 1K page size          2Ch
50.0ns    DDR3-1066, 2K page size          90h
30.0ns    DDR3-1333, 1K page size          F0h
45.0ns    DDR3-1333, 2K page size          68h
30.0ns    DDR3-1600, 1K page size          F0h
40.0ns    DDR3-1600, 2K page size          40h
Byte 30  （DRAM颗粒可选特）
SDRAM Optional features 
This byte defines the optional drive strengths supported by the SDRAMs on this module. This information can be found from the SDRAM data sheet.
RZQ/6  supported  RZQ/7  supported                    03h
RZQ/6  supported  RZQ/7  not supported              01h
RZQ/6  not supported  RZQ/7  supported              02h
Byte 31  （DRAM热控和刷新功能）
SDRAM thermal and refresh options
This byte describes the module抯 supported operating temperature ranges and refresh options. These values come from the DDR3 SDRAM data sheet. The information includes On-die Thermal sensor support, ASR Refresh support, 1X or 2X Temperature Refresh Rate support as well as the Extended Temperature Range.
(When CST EZ-SPD Programmer is used: Simply select all supported options from table. It automatically calculate the hex value based on the 2 byte binary number)
Byte 32  Module thermal sensor  （模组热传感集成）
未使用热感  00h
使用热感    80h
Byte 33  DRAM内核数目
单核 00h
非单核 80h
Byte 34－59  预留
Reserved, General Section            00h
Byte 60
Module Nominal Height  内存模组高度
Under or equal 15mm                    00h
Between 15 and 16mm                  01h
Between 16 and 17mm                  02h
Between 17 and 18mm                  03h
Between 18 and 19mm                  04h
Between 19 and 20mm                  05h
Between 20 and 21mm                  06h
Between 21 and 22mm                  07h
Between 22 and 23mm                  08h
Between 23 and 24mm                  09h
Between 24 and 25mm                  0Ah
Between 25 and 26mm                  0Bh
Between 26 and 27mm                  0Ch
Between 27 and 28mm                  0Dh
Between 28 and 29mm                  0Eh
Between 29 and 30mm                  0Fh
Between 30 and 31mm                  10h
Between 31 and 32mm                  11h
Between 32 and 33mm                  12h
Between 33 and 34mm                   13h
Between 34 and 35mm                  14h
Between 35 and 36mm                  15h
Between 36 and 37mm                  16h
Between 37 and 38mm                  17h
Between 38 and 39mm                  18h
Between 39 and 40mm                   19h
Between 40 and 41mm                  1Ah
Between 41 and 42mm                  1Bh
Between 42 and 43mm                  1Ch
Between 43 and 44mm                  1Dh
Between 44 and 45mm                  1Eh
Over 45mm                                  1Fh
Byte 61
Module Mechanical Maximum Thickness  内存最大厚度
This byte defines the maximum thickness in millimeters of the fully assembled module including heat spreaders and any other components. It is in two parts; the front thickness (from PCB surface) and the back thickness (from PCB surface).
(When CST EZ-SPD Programmer is used: Simply selected by number between 1-15mm for front thickness and by number between 1-15mm for back thickness. Program automatically converts these thickness number into 2 byte hex code.)
Smaller or equal to 1mm on both front and back  00h
1 to 2 mm on both front and back                     11h
2 to 3 mm on both front and back                      22h
3 to 4 mm on both front and back                      33h
2 mm on front 1 mm max on back                        01h
3 mm on front 1 mm max on back                        02h
4 mm on front 1 mm max on back                        03h   
Byte 62
Reference Raw Card Used  使用的Raw card类型
This Byte indicates which JEDEC reference design raw card was used as the basis for the module assembly. It includes Raw Card designator and Revision number.
(When CST EZ-SPD Programmer is used: Simply select by number on revision code. Select Raw Card number by alphabetic code. Program automatically calculates the 2 byte Hex number.) 
Raw Card  A  rev. 0      00h ,         rev. 1        20h ,        rev. 2      40h ,         rev. 3        60h     
Raw Card  B  rev. 0      01h ,        rev. 1         21h ,         rev. 2      41h ,        rev. 3        61h
Raw Card  C  rev. 0      02h ,        rev. 1        22h ,        rev. 2      42h ,        rev. 3        62h
Raw Card  D  rev. 0      03h ,        rev. 1        23h ,        rev. 2      43h ,        rev. 3        63h
Raw Card  E  rev. 0      04h ,        rev. 1         24h ,        rev. 2      44h ,        rev. 3        64h
Raw Card  F  rev. 0      05h ,          rev. 1         25h ,         rev. 2      45h ,        rev. 3        65h
Raw Card  G  rev. 0      06h ,        rev. 1        26h ,        rev. 2      46h ,        rev. 3        66h
Raw Card  H  rev. 0      07h ,        rev. 1        27h ,        rev. 2      47h ,        rev. 3        67h
Raw Card  J  rev. 0       08h ,        rev. 1        28h ,        rev. 2      48h ,        rev. 3        68h
Raw Card  K  rev. 0      09h ,        rev. 1         29h ,        rev. 2      49h ,        rev. 3         69h
Raw Card  L   rev. 0      0Ah ,         rev. 1         2Ah ,        rev. 2      4Ah ,        rev. 3        6Ah
Raw Card  M   rev. 0     0Bh ,        rev. 1         2Bh ,        rev. 2     4Bh ,        rev. 3         6Bh
Raw Card  N  rev. 0      0Ch ,         rev. 1        2Ch ,        rev. 2      4Ch ,        rev. 3         6Ch
Raw Card  P  rev. 0      0Dh ,         rev. 1         2Dh ,        rev. 2      4Dh ,        rev. 3        6Dh
Raw Card  R  rev. 0      0Eh ,        rev. 1         2Eh ,        rev. 2      4Eh ,        rev. 3        6Eh
Raw Card  T  rev. 0      0Fh ,         rev. 1         2Fh ,         rev. 2      4Fh ,         rev. 3        6Fh
Raw Card  U  rev. 0      10h ,         rev. 1         30h ,         rev. 2      50h ,         rev. 3        70h
Raw Card  V  rev. 0      11h ,         rev. 1         31h ,         rev. 2      51h ,         rev. 3         71h
Raw Card  W  rev. 0    12h ,          rev. 1         32h ,        rev. 2      52h ,         rev. 3        72h
Raw Card  X  rev. 0      13h ,          rev. 1         33h ,         rev. 2      53h ,         rev. 3         73h
Raw Card  Y  rev. 0     14h ,          rev. 1         34h ,        rev. 2      54h ,         rev. 3        74h
Raw Card  Z  rev. 0     15h ,          rev. 1         35h ,         rev. 2      55h ,          rev. 3        75h
Byte 63
Address Mapping from Edge Connector to DRAM  地址镜像
For ease of module PCB layout, sometimes 搈irror?address mapping is used. 揗irror?address is to flip the address line sequence on the 2nd rank of the module. This byte describes the connection of edge connector pins for address bits to the corresponding input pins of the DDR3 SDRAMs. 
Rank 1 Mapping   
Standard            00h
Mirrored            01h
Byte 64-116
Reserved                          00h
Byte 117
Module Manufacturer ID Code, Least Significant Byte
This code is obtained through manufacturer抯 registration with JEDEC (the standard setting committee). A small fee is charged by JEDEC to support and maintain this record. Please contact JEDEC office.
Byte 117 is the least significant byte while byte 118 is the most significant byte. If the ID is not larger than one byte (in hex), byte 118 should be filled with 00h.
Byte 118
Module Manufacturer ID Code, Most Significant Byte
This code is obtained through manufacturer抯 registration with JEDEC (the standard setting committee). A small fee is charged by JEDEC to support and maintain this record. Please contact JEDEC office.
Byte 117 is the least significant byte while byte 118 is the most significant byte. If the ID is not larger than one byte (in hex), byte 118 should be filled with 00h.
Byte 119
Module Manufacturing Location
Optional manufacturer assigned code.
Byte 120
Module Manufacturing Date
Byte 120 is for the year.
(When CST EZ-SPD Programmer is used: User selects the year to automatically enter the year code in hex.)
Byte 121
The week of the year, 1 to 52.
(When CST EZ-SPD Programmer is used: The program should automatically calculate the week of the year once a day on the calendar is click selected and 揙K?by the user. It will also automatically convert to the proper SPD hex code)
Byte 122-125
Module Serial Number
Optional manufacturer assigned number.
On the Serial Number setting, JEDEC has no specification on data format nor dictates the location of the Most Significant Bit. Therefore, it抯 up to the individual manufacturer to assign his numbering system.(All CST testers and EZ-SPD programmers have the option for the user to select either byte 122 or 125 as the MSB (most significant bit). The tester assumes the use of ASCII format, which is the most commonly used. The CST testers also have the function to automatically increment the serial number on each module tested.)
Byte 126-127  CRC校验
SPD Cyclical Redundancy Code (CRC)
This two-byte field contains the calculated CRC for previous bytes in the SPD. A certain algorithm and data structures are to be followed in calculating and checking the code. Bit 7 of Byte 0 indicates which bytes are covered by the CRC.
(When CST EZ-SPD Programmer is used: The CST tester automatically calculates the CRC for you based on information of Byte 0 ?Byte 125.)
Byte 128-145
Module Part Number
The manufacturer抯 part number is written in ASCII format within these bytes.
Byte 128 is the most significant digit in ASCII while byte 145 is the least significant digit in ASCII. Unused digits are coded as ASCII blanks (20h).
(When CST EZ-SPD Programmer is used: Simply click the button at the right of Byte 128 to open an edit window, input the manufacturer抯 PN (Maximum 18 digits). The software will automatically translate it into ASCII and write them into Bytes 128-145.)
Byte 146-147
Module Revision Code
Optional Manufacturer Assigned Code
Byte 148
DRAM Manufacturer ID Code, Least Significant Byte
This code is obtained through manufacturer抯 registration with JEDEC (the standard setting committee). A small fee is charged by JEDEC to support and maintain this record. Please contact JEDEC office. Reference to JEDEC document JEP-106 for more detail.
Byte 148 is the least significant byte while byte 149 is the most significant byte. If the ID is not larger than one byte (in hex), byte 149 should be filled with 00h.
Byte 149
DRAM Manufacturer ID Code, Most Significant Byte
This code is obtained through manufacturer抯 registration with JEDEC (the standard setting committee). A small fee is charged by JEDEC to support and maintain this record. Please contact JEDEC office. Reference to JEDEC document JEP-106 for more detail.
Byte 148 is the least significant byte while byte 149 is the most significant byte. If the ID is not larger than one byte (in hex), byte 149 should be filled with 00h. 
Byte 150-175
Manufacturer抯 Specific Data
Optional manufacturer assigned code. The module manufacturer may include any additional information desired into the module within these locations.
Byte 176-255
Open for Customer Use
Optional customer assigned codes. These bytes are unused by the manufacturer and are open for customer use.
Final Note:
Everything in the above article and more are now implemented into the CST EZ-SPD DDR3 Programmer software. The new features are:
1. Pop up window of explanation on each Byte.
2. Clickable selection right from the illustration window.
3. Auto CRC checksum on byte 126 and byte 127.
4. Text input on "manufacturer code" and "serial number". User define MSB/LSB format.
5. Auto JEDEC week and year coding from PC clock.
6. Software write protect function.