REALTEK SINGLE CHIP
5-PORT 10/100 MBPS SWITCH CONTROLLER
RTL8305SB
1. Features (2)
2. General Description (3)
3. Block Diagram (4)
4. Pin Assignments (5)
5. Pin Descriptions (7)
5.1 Media Connection Pins (7)
5.2 Configuration Pins (7)
5.3 Port4 External MAC Interface Pins (8)
5.4 Miscellaneous Pins (13)
5.5 Per Port LED Pins (14)
5.6 Power Pins (15)
5.7 Reserved Pins (16)
5.8 Serial EEPROM and SMI Pins (16)
5.9 Strapping Pins (17)
5.10 Port Status Strapping Pins (19)
6. Register Description (21)
6.1 PHY0 to 4: PHY Register of Each Port (22)
6.1.1 Register0: Control Register (22)
6.1.2 Register1: Status Register (23)
6.1.3 Register4: Auto-Negotiation Advertisement Register (23)
6.1.4 Register5: Auto-Negotiation Link Partner Ability Register (24)
6.1.5 Register6: Auto-Negotiation Expansion Register (24)
6.2 PHY0: EEPROM Register0 (25)
6.2.1 Register16: EEPROM Byte0 and 1 Register (25)
6.2.2 Register17: EEPROM Byte2 and 3 Register (25)
6.2.3 Register18~20: EEPROM EthernetID Register.25
6.2.4 Register21: EEPROM Byte10 and 11 Register.26
6.2.5 Register22: EEPROM Byte12 and 13 Register.26
6.3 PHY1: EEPROM Register1 (27)
6.3.1 Register16~23: EEPROM (Byte 14~29) Register (27)
6.3.2 Register24~31: EEPROM VLAN (Byte 30~44) Register (27)
6.4 PHY2: Pin & EEPROM Register (28)
6.4.1 Register16: Pin Register (28)
6.4.2 Register17: Pin & EEPROM Register for VLAN (29)
6.5 PHY3: Port Control Register (30)
6.5.1 Register16: Port Control Register (30)
6.5.2 Register17: EEPROM (Byte 46) Register (31)
6.5.3 Register18~20: EEPROM (Byte 47~52) Register (31)
7. Functional Description (32)
7.1 Switch Core Functional Overview (32)
7.1.1 Application (32)
7.1.2 Port4 (32)
7.1.3 Port Status Configuration (36)
7.1.4 Enable Port (36)
7.1.5 Flow Control (37)
7.1.6 Address Search, Learning and Aging (38)
7.1.7 Address Direct Mapping Mode (38)
7.1.8 Half Duplex Operation (38)
7.1.9 Inter-Frame Gap (38)
7.1.10 Illegal Frame (38)
7.2 Physical Layer Functional Overview (39)
7.2.1 Auto-Negotiation for UTP (39)
7.2.2 10Base-T Transmit Function (39)
7.2.3 10Base-T Receive Function (39)
7.2.4 Link Monitor (39)
7.2.5 100Base-TX Transmit Function (39)
7.2.6 100Base-TX Receive Function (39)
7.2.7 100Base-FX (39)
7.2.8 100Base-FX Transmit Function (40)
7.2.9 100Base-FX Receive Function (40)
7.2.10 100Base-FX Far-End-Fault-Indication (FEFI)40
7.2.11 Reduced Fiber Interface (40)
7.2.12 Power Saving Mode (40)
7.2.13 Reg0.11 Power Down Mode (40)
7.2.14 Crossover Detection and Auto Correction (41)
7.2.15 Polarity Detection and Correction (41)
7.3 Advanced Functional Overview (42)
7.3.1 Reset (42)
7.3.2 Setup and Configuration (42)
7.3.3 Example of Serial EEPROM: 24LC02 (43)
7.3.4 24LC02 Device Operation (43)
7.3.5 SMI (44)
7.3.6 Head-Of-Line Blocking (44)
7.3.7 802.1Q Port Based VLAN (44)
7.3.8 QoS Function (46)
7.3.9 Insert/Remove VLAN Priority Tag (46)
7.3.10 Filtering/Forwarding Reserved Control Frame47
7.3.11 Broadcast Storm Control (47)
7.3.12 Broadcast In/Out Drop (47)
7.3.13 Loop Detection (48)
7.3.14 MAC Loopback return to External (49)
7.3.15 Reg0.14 PHY Loopback return to Internal (50)
7.3.16 LED (50)
7.3.17 2.5V Power Generation (52)
7.3.18 Crystal/Oscillator (52)
8. Serial EEPROM Description (53)
9. Electrical Characteristics (57)
9.1 Absolute Maximum Ratings: (57)
9.2 Operating Range: (57)
9.3 DC Characteristics (57)
9.4 AC Characteristics (58)
9.5 Digital Timing Characteristics (59)
9.6 Thermal Data (59)
10. Application Information (60)
10.1 UTP (10Base-T/100Base-TX) Application (60)
10.2 100Base-FX Application: (62)
11. System Application Diagram (63)
12. Design and Layout Guide (64)
13. Mechanical Dimensions (65)
1. Features
5-port integrated switch controller with memory and transceiver for 10Base-T and 100Base-TX with
5-port 10/100M UTP or
4-port 10/100M UTP + 1-port MII/SNI
Supports PHY mode MII /SNI for router applications and MAC mode MII for HomePNA or VDSL solutions  All ports support 100Base-FX with optional flow control enable/disable and full/half duplex setting
Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding
Fully compliant with IEEE 802.3/802.3u
auto-negotiation function
Built-in high efficiency SRAM for packet buffer and 1K entry look-up table, and 16 entry CAM
Supports broadcast storm filtering function
Supports IEEE802.3x full duplex flow control and back pressure half duplex flow control
Supports SMI (Serial Management Interface:
MDC/MDIO) for programming and diagnostics
Supports loop detection function with one LED to indicate the existence of loop
Supports loopback function for diagnosis
Flexible 802.1Q Port based VLAN. Up to 5 VLAN  Supports 802.1Q tag VLAN function
Supports ARP VLAN for broadcast packets
Supports Leaky VLAN for unicast packets  Supports QoS function on each port:
QoS based on: (1) Port-based (2) VLAN tag
(3) TCP/IP header’s TOS/DS
Supports two level priority queues
Weighted round robin service
Supports VLAN priority tag Insert/Remove function  Optional 1536 or 1552 byte maximum packet length  Supports reserved control frames (DID=
0180C2000003~0180C200000F) filtering function  Flexible LED indicators for link, activity, speed, full/half duplex and collision
LEDs blink upon reset for LED diagnostics
Supports two Power Reduction methods:
Power saving mode by cable detection
Power down mode (by PHY register 0.11)
Robust baseline wander correction for improved 100BASE-TX performance
Optional Crossover Detection and Auto Correction function
Physical layer port Polarity Detection and Correction function
Optional EEPROM interface for configuration
25MHz crystal or OSC input. Single 3.3V power system like by translating of an external transistor
0.25 µm, CMOS technology, 3.3V/2.5V with 3.3V
input tolerant, 128 pin PQFP package
2. General Description
The RTL8305SB is a Fast Ethernet switch, which integrates memory, five MACs, and five physical layer transceivers for 10Base-T and 100Base-TX operation into a single chip. All ports support 100Base-FX, which share pins (TX+-/RX+-) with UTP ports and need no SD+/- pins, a development using Realtek proprietary technology. Due to the lack of auto-negotiation in 100Base-FX applications, t
he RTL8305SB can be forced into half or full duplex mode and can enable or disable flow control in fiber mode.
The five ports are separated into 3 groups (GroupX/GroupY/Port4) for flexible port configuration using strapping pins upon reset. The SetGroup pin is used to select port members in GroupX and GroupY. While the port members is determined, you can use mode selection pin (GxMode/Gymode/P4Mode[1:0]) to select operating interfaces such as 10/100Base-TX, 100Base-FX. Each group has 4 pins to select initial port status (ANEG/Force, 100/10, Full/Half, Enable/Disable Flow Control) upon reset. Upon reset, in addition to using strapping pins, the RTL8305SB also can be configured with an EEPROM or read/write operation by a CPU through the MDC/MDIO interface.
The fifth port (port 4) supports an external MAC interface, which can be set to PHY mode MII, PHY mode SNI, or MAC mode MII to work with a routing engine, HomePNA or VDSL transceiver. In order to accomplish diagnostics in complex network systems, the RTL8305SB also provides a loopback feature in each port for a variable CPU system.
The RTL8305SB contains a 1K entry address look-up table and supports a 16 entry CAM to avoid hash collisions and to maintain forwarding performance. The RTL8305SB supports IEEE 802.3x full du
plex flow control and back- pressure half duplex flow control. The broadcast storm filtering function is provided to filter unusual broadcast storm issues and has an intelligent switch engine to prevent Head-Of -Line blocking problems.
The RTL8305SB supports 5 groups of VLANs which can be configured with port based VLAN and/or 802.1Q tag VLAN. ARP broadcast and Leaky VLAN are also supported for advanced applications.
The RTL8305SB supports several types of QoS functions with two level priority queues to improve multi-media or real-time networking applications. The QoS functions are based on: 1) Port based priority; 2) 802.1Q VLAN priority tag; 3) The TOS/DS (DiffServ) field of TCP/IP. In order to avoid the flow control function effecting the quality of high priority frames, the RTL8305SB supports an intelligent flow control for high priority frames by setting DisFCAutoOff to automatically turn off flow control for 1~2 seconds whenever the congestion port receives high priority frames. When the QoS function is enabled, a VLAN tag can be inserted or removed at the output port. The RTL8305SB will insert a VLAN priority-tag (VID=0x000) for untagged frames or remove the tag for all tagged frames.
Maximum packet length can be 1536 or 1552 bytes according to the initial configuration (strapping upon reset). The filtering function is supported for the 802.1D specified reserved group MAC addresse
s (01-80-C2-00-00-03 to 01-80-C2-00-00-0F). The RTL8305B provides flexible LED functions for diagnostics, which include: 1) Four combinations of link, activity, speed, duplex and collision which are designed for convenient LED displays, such as bi-color LEDs; 2) Reset blinking; 3) Blinking time selection. The RTL8305SB also provides a loop detection function and alarm, for network existence notification, with an output pin which can be designed as a visual LED or a status input pin for a CPU.
The RTL8305SB implements a power saving mode on a per port basis. One port automatically enters power saving mode 10 seconds after the cable is disconnected from it. The RTL8305SB also implements a power down mode on a per port basis. Users can set MII Reg.0.11 to force the corresponding port to enter the power down mode, which disables all transmit/receive functions, except SMI (MDC/MDIO management interface).
Each physical layer channel of the RTL8305SB consists of a 4B5B encoder/decoder, a Manchester encoder/decoder, a scrambler/descrambler, a transmit output driver, output wave shaping filters, a digital adaptive equalizer, a PLL circuit and a DC restoration circuit for clock/data recovery. Friendly crossover auto detection and correction functions are also supported for easy cable connection.
The integrated chip benefits from low power consumption, advanced functions with flexible configurations for 5-port SOHO switch, Home Gateway, xDSL/Cable router, and other IA applications.
3. Block Diagram
4. Pin Assignments
LED_SPD[2]/BCI N D ROP
G ND
LED _ACT[2]/ENFO RW A RD
LED _D U P[2]/G YFU LL LED _SPD [1]/G XFU LL LED_A CT[1]/G Y SPD 100LED_D UP[1]/G X SPD 100V DD
LED _SPD [0]/G YA N EG
LED _A CT[0]/G XA N EG V D D
I BREF A G N D A G N D VCTRL LED_SPD [4]/D I SLEA K Y
LED _A CT[4]/DI SA RP LED _D U P[4]/48PA SS1LED _SPD [3]/EN D EFER LED _A CT[3]/RESERV ED2LED _DU P[3]/M AX 1536RV DD RX I P[0]
RXI N [0]A V DD LED _DU P[0]/P4A N EG E N _R S T _B L N K D I S P O R T P R I [3]E N _A U T O X O V E R M TXD[1]/PR XD [1]/LED M O D E[1]M R XD[0]/PTXD [0]M TXD[0]/PR XD [0]/LED M O D E[0]D I S B R D C T R L G X E N F C G Y E N F C
L E D _B L N K _T I M E D I S P O R T P R I [0]Q W E I G H T [1]D I S P O R T P R I [1]D I S P O R T P R I [2]V D D D I S P O R T P R I [4]M R X D [3]/P T X D [3]C K 25M O U T S E L _M I I M A C #/D I S D S P R I V D D R E S E R V E D 1S C L _M D C E N E E P R O M M R X D [2]/P T X D [2]G N D
M TXD[3]/PR XD [3]/P4I R TAG [1]M R XC/PTXC M TXD[2]/PR XD [2]/P4I R TAG [0]M C O L/PC O L M R XDV/PTXEN VD D M R XD[1]/PTXD [1]G N D VD D
P4SPDSTA/P4SPD 100P4D U PSTA/P4FU LL M G N D
P4LN KSTA#M TXC/PR XC M TXEN/PRXD V VD D X1P4FLCTR L/P4EN FC X2G N Dnegotiation auto
R ESET#R TT2R TT3M V D D G N D T E S T #L O O P L E D #/D I S T A G P R I L E D _A D D [2]/S E T G R O U P L E D _A D D [0]/D I S F C A U T O O F F G N D L E D _A D D [3]/G X M O D E L E D _A D D [1]/D I S V L A N P 4M O D E [0]P 4M O D E [1]L E D _A D D [4]/G Y M O D E V D D Q W E I G H T [0]G N D E N A N E G _B K P R S T G N D R X I N [1]R X I P [1]R G N D T G N D T X O P [1]T X O N [1]T V D D T V D D T X O N [0]T X O P [0]R V D D T X O N [3]T V D D T V D D T X O N [2]T X O P [2]T G N D R G N D R X I P [2]R X I N [2]R V D D T X O P [3]T G N D R G N D R X I P [4]R X I N [4]R V D D R V D D R X I N [3]R X I P [3]R G N D T G N D T X O P [4]T V D D T X O N [4]R G N D S D A _M D I O
128 Pin RTL8305SB

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