摘要
摘要
射频LDMOS器件作为功率集成电路中的核心器件，近年来已经成为国内外众多器件研究者的研究热点，由于横向高压功率器件中击穿电压与比导通电阻之间的严重矛盾关系一直限制着RF LDMOS在高压大电流环境下的应用，同时，随着民用移动
通信技术和军用雷达技术这些年的飞速发展，人们对无线信号的传输和传输质量的要求也在变高。在移动通信和军用雷达中，射频功率放大器作为信号发射机中的关键组成部分，它直接决定了无线信号的收发质量和其传输的距离，而射频功率放大器的性能又与其核心部件——射频功率器件密切相关。所以现在针对射频器件的研究方向主要集中在设计并制造出性能更加优越的射频功率器件，即让器件拥有更高的耐压、更高的工作频率以及较低的功耗，本论文就是基于射频LDMOS器件展开的研究，首先研究该器件的基本工作原理，然后利用仿真软件ISE-TCAD具体分析器件中的各部分参数对器件击穿特性、输出特性以及频率特性的影响，最后在上述工作的基础上对射频LDMOS器件结构进行优化，使其拥有更优越的性能。
首先，本文提出了具有部分阶梯埋层的RF LDMOS器件新结构，该结构将器件内部的SOI埋层做成阶梯状来调制器件的表面电场，优化阶梯的结构使器件的横向电场分布趋于均匀提高器件的击穿电压，同时
利用阶梯状的SOI埋层来减小器件内部的源漏寄生电容，进一步提高了器件的截止频率和输出功率。通过仿真软件ISE-TCAD 仿真分析得到，本文建立的表面电场分布模型与仿真结果基本吻合，新电场峰的获得从本质上解释了阶梯埋氧层对表面电场的调制效应。该器件在保证其比导通电阻不会增加的情况下，充分利用了阶梯SOI层的电场调制效应，提高了器件的击穿电压，与同尺寸的普通PSOI RF LDMOS器件相比，击穿电压从100.1V提高到123.2V，提高了23.08%，同时由于阶梯埋氧层减小了器件的寄生电容，所以该器件的截止频率f T 与普通PSOI RF LDMOS相比也提高了18.09%。
其次，本文还提出了漂移区加电极的硅基折叠射频LDMOS器件，该器件结构是在FALDMOS（LDMOS with a folded-accumulation layer：具有折叠积累层的LDMOS）器件的基础上，在器件的漂移区上面增加了氧化层电极，并对该电极施加一定的电压，这样做是在FALDMOS器件低导通电阻的基础上，利用在器件漂移区上面加电极来提高器件的跨导，进一步提高器件的特征频率，让射频LDMOS器件可以很好地往高频低功耗领域发展，通过仿真研究发现，漂移区加电极的硅基折叠射频LDMOS器件的比导通电阻与FALDMOS相比增加了6.2%，但是与同尺寸RF LDMOS相比依旧减小了36.24%，同时其特征频率达到1.17GHz，是FALDMOS器件的2.2倍，是普通
RF LDMOS器件的1.95倍。该器件如果应用在射频功率放大器电路中，不仅可以保证器件的功耗较低，同时也具有较好的频率特性。
modulate关键词：射频LDMOS，寄生电容，特征频率，击穿电压，折叠硅
ABSTRACT
ABSTRACT
RF LDMOS device as the core of power integrated circuits, in recent years, it has become a research hotspot for large number of domestic and foreign device researchers, because of the serious contradiction between the breakdown voltage and the on-resistance in the transverse high-voltage power device, the application of RF LDMOS in high voltage and high current environment has been restricted. At the same time, with the rapid development of civil mobile communication technology and military radar technology, the quality of wireless signal transmission and transmission quality is becoming higher. In the mobile communication base station and military radar, RF power amplifier is a key component in the signal transmitter, which directly determines the quality of the wireless signal receiving and transmission distance, and the performance of the RF power amplifier and its core components--RF power transistors are closely related. So now the research direction for the RF device is mainly focused on the design and manufacture of RF power devices with more superior performance, let the device has higher breakdown voltage, higher frequency and lower pow
er consumption, this thesis is based on the development of RF LDMOS devices. Firstly, the basic working principle of the device is studied. Then, the effects of various parameters of the device on the breakdown characteristics, output characteristics and frequency characteristics of the device are analyzed by using the simulation software ISE-TCAD. Finally, based on the above work, the structure of RF LDMOS devices is optimized to make it more superior.
Firstly, a new structure of RF LDMOS device with partial stepped buried layer is presented, in this structure, the SOI buried layer inside the device is stepped to modulate the surface electric field of the device, the structure of the step is optimized so that the transverse electric field distribution of the device tends to be uniform to improve breakdown voltage of the device, while the stepped SOI buried layer is used to reduce the source-drain parasitic capacitance within the device, and furtherly cut-off frequency and output power of the device are improved. Through the simulation analysis with software ISE-TCAD simulation, the surface electric field distribution model prensented in this paper is consistent with the simulation results, and the acquisition of the new electric field peak explains the modulation effect of the buried oxygen layer on the surface electric field. The device can make full use of the electric field modulation effect of the stepped SOI layer
and improve the breakdown voltage of the device when the specific resistance of the device is not increased. Compared with the same size PSOI RF LDMOS device, the breakdown voltage increases from 100.1V to 123.2V, which is improved by 23.08% , and the cut-off frequency f T of the device is increased by 18.09% because the step buried layer reduces the parasitic capacitance of the device.
Secondly, this paper also presents a folded RF LDMOS on silicon substrate with drift region electrodes, this device is on the basis of the FALDMOS device, the structure of the device is added with an oxide electrode on the drift region, and a certain voltage is applied to the electrode. On the basis of the low on resistance of the FALDMOS device, do it in this way the structure can be used to increase the transconductance of the device, and further improve the characteristic frequency of the device, so that RF LDMOS devices can be well developed in the field of high frequency and low power consumption. The simulation results show that the on-resistance of silicon folded RF LDMOS devices with the drift region of the electrode compared with FALDMOS increased by 6.2%, but compared with the same size of RF LDMOS its still decreased by 36.24%, at the same time, the characteristic frequency of the device reaches 1.17GHz, which is 2.2 times of the FALDMOS device, and is 1.95 times of the ordinary RF LDMOS device. If this device is used in the RF power amplifier circuit, it can not only ensure the low power consumption of the device, but also has good frequency characteristics.
Keywords: Radio Frequency of the Lateral Double-Diffused Metal-Oxide-Semiconductor, Parasitic Capacitance, Characteristic Frequency, Breakdown V oltage, Folded Silicon
插图索引
插图索引
图2.1射频LDMOS器件基本结构 (7)
图2.2单RESURF技术原理图 (9)
图2.3Double RESURF LDMOS器件结构 (10)
图2.4场板及其表面电场分布图 (11)
图2.5REBULF LDMOS结构剖面示意图 (11)
图2.6不同漂移区长度时的I-V曲线 (13)
图2.7RF LDMOS的小信号等效电路图 (13)
图2.8跨导与栅氧化层厚度之间的关系 (15)
图2.9栅漏寄生电容C gd随栅氧化层厚的的变化 (16)
图2.10f T和f max随栅氧化层厚度的变化 (16)
图2.11C gd随沟道掺杂浓度的变化 (17)
图2.12C gd随漂移区掺杂浓度的变化 (17)
图2.13跨导g m随漂移区掺杂浓度的变化 (18)
图2.14特征频率f T随漂移区掺杂浓度的变化 (18)
图2.15栅漏电容C gd和特征频率f T随漂移区结深的变化 (19)
图2.16C gd和f T随V DS的变化 (20)
图2.17SOI LDMOS器件结构 (21)
图2.18部分SOI射频LDMOS结构 (21)
图2.19射频LDD LDMOS器件结构 (22)
图2.20漂移区分区掺杂的RF LDMOS器件结构 (22)
图2.21具有接地法拉第罩结构的RF LDMOS器件[47] (22)
图2.22具有接地场板结构的LDMOS晶体管[47] (23)
图3.1PSOI RF LDMOS和具有部分阶梯埋氧层的RF LDMOS器件结构 (25)
图3.2具有部分阶梯埋层的RF LDMOS器件表面电场对比图 (28)
图3.3击穿电压和漂移区比导通电阻与L d的关系 (29)
图3.4栅漏寄生电容与L d的关系 (29)
图3.5器件的特征频率与L d的关系 (30)
图3.6埋氧层厚度t ox对器件击穿电压的影响 (30)
图3.7C gd和跨导随阶梯埋层厚度的变化趋势 (31)
图3.8特征频率随阶梯埋层厚度的变化趋势 (31)
图3.9器件表面电场强度、击穿电压和逼到通电阻与埋层阶梯个数的关系. 32图3.10跨导和C gd随埋层阶梯个数的变化 (33)
图3.11特征频率f T随埋层阶梯个数的变化 (33)